Damage Implantation of a Cap Layer

ABSTRACT

A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls, The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.

CROSS REFERENCE TO RELATED APPLICATIONS

This is a division of and claims priority to U.S. application Ser. No.12/817,829, filed on Jun. 17, 2017, which is a division of and claimspriority to U.S. application Ser. No. 11/771,269, filed on Jun. 29,2007, that is now U.S. Pat. No. 8,859,377, granted Oct. 14, 2014, thecontents of all are incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

This invention relates to the fabrication of a semiconductor transistorusing a cap layer during the source/drain anneal process.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a semiconductor structure inaccordance with the present invention,

FIGS. 2A-2E are cross-sectional diagrams of a process for forming atransistor in accordance with the present invention.

FIGS. 3A-3E are cross-sectional diagrams of an alternative process forforming a transistor in accordance with an alternative embodiment of thepresent invention,

FIGS. 4A-4F are cross-sectional diagrams of another alternative processfor forming a transistor in accordance with an alternative embodiment ofthe present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is described with reference to the attachedfigures, wherein like reference numerals are used throughout the figuresto designate similar or equivalent elements. The figures are not drawnto scale and they are provided merely to illustrate the invention.Several aspects of the invention are described below with reference toexample applications for illustration. It should be understood thatnumerous specific details, relationships, and methods are set forth toprovide a full understanding of the invention. One skilled in therelevant art, however, will readily recognize that the invention can bepracticed without one or more of the specific details or with othermethods. In other instances, well-known structures or operations are notshown in detail to avoid obscuring the invention. The present inventionis not limited by the illustrated ordering of acts or events, as someacts may occur in different orders and/or concurrently with other actsor events. Furthermore, not all illustrated acts or events are requiredto implement a methodology in accordance with the present invention.

Referring to the drawings, FIG. 1 is a cross-sectional view of a portionof a semiconductor wafer 10 in accordance with the present invention. Inthe example application, CMOS transistors 60, 70 are formed within asemiconductor substrate 20 having a p-well 30 containing the NMOStransistor 70 and an n-well 40 containing PMOS transistor 60. Thepotions of the semiconductor wafer 10 that are not shown may contain anycombination of active and passive devices, such as additional CMOS,BiCMOS and bipolar junction transistors—as well as capacitors,optoelectronic devices, inductors, resistors, and diodes.

The CMOS transistors 60, 70 are electrically insulated from other activedevices located within the semiconductor wafer 10 (not shown) by shallowtrench isolation structures 50 formed within the semiconductor substrate20; however, any conventional isolation structure may be used such asfield oxide regions or implanted isolation regions. The semiconductorsubstrate 20 may be a single-crystalline substrate that is doped withn-type and p-type dopants; however, it may also be a silicon germanium(“SiGe”) substrate, a silicon-on-insulator (“SOI”) substrate, or asingle-crystalline substrate having an epitaxial silicon layer that isdoped with n-type and p-type dopants.

Transistors, such as CMOS transistors 60, 70, are generally comprised ofa gate, source, and drain. More specifically, as shown in FIG. 1, theactive portion of the CMOS transistors are comprised of source/drainregions 80, source/drain extension regions 90, a gate stack that iscomprised of a gate dielectric 100 and gate electrode 110, and a channelregion 190 located under the gate dielectric 100 and near the surface ofthe substrate.

The example PMOS transistor 50 is a p-channel MOS transistor. Thereforeit is formed within an n-well region 40 of the semiconductor substrate20, In addition, the deep source/drain regions 80 and the extensionregions 90 have p-type dopants, such as boron. The extension regions 90may be lightly doped (“LDD”), medium doped (“MDD”), or highly doped(“HDD”), However, sources/drain regions 80 are usually heavily doped.The PMOS gate stack is comprised of a p-type doped polysilicon electrode110 and gate oxide dielectric 100. However, it is within the scope ofthe invention for the PMOS gate stack to have a metal electrode 110instead of a polysilicon electrode 110.

The example NMOS transistor 70 is an n-channel MOS transistor. Thereforeit is formed within a p-well region 30 of the semiconductor substrate20. In addition, the deep sources and drains 80 and the source and drainextensions 90 have n-type dopants such as arsenic, phosphorous,antimony, or a combination of n-type dopants. The extension regions 90may be LDD, MDD, or HDD. However, sources/drain regions 80 are usuallyheavily doped. The NMOS gate stack is comprised of an n-type dopedpolysilicon electrode 110 and gate oxide dielectric 100. However, it iswithin the scope of the invention for the NMOS gate stack to have ametal electrode 110 instead of a polysilicon electrode 110.

The extension regions 90 are formed using the gate stack 100, 110 as amask in the example embodiment. However, it is within the scope of theinvention to form the extension regions 90 using the gate stack plusextension sidewalls that are located proximate the gate stack (notshown) as a mask. An offset structure comprising source/drain sidewalls130 is used during fabrication to enable the proper placement of thesource/drain regions 80. More specifically, the sources/drain regions 80are formed with the gate stack and source/drain sidewalls 130 as a mask.

In the example application shown in FIG. 1, a sacrificial conformal caplayer 120 (sometimes called a “stress memorization layer”) covers thePMOS and NMOS transistors. The cap layer 120 is used during thefabrication process to impart (or “memorize”) stress into the gateelectrode 110 during the source/drain anneal process. In the On-state ofthe transistor, the stress that is memorized in the poly gate electrode110 is transferred to the channel region 190, thereby improvingtransistor performance by improving the carrier mobility in the channelregion (resulting in an improved transistor drive current without anincrease in leakage current).

The cap layer 120 is preferably SiN; however, the cap layer 120 may becomprised of any suitable material such as SiON, SIC, SiOCN, or SiOC. Inaddition, the cap layer 120 is preferably 300-6001 Å thick; however, thecap layer may be any suitable thickness between 50-1000 Å. The cap layer120 in the example application is formed by a plasma enhanced chemicalvapor deposition (“PECVD”) process (using silane and ammoniaprecursors); however, the cap layer 120 may be formed with any suitableprocess such as chemical vapor deposition (“CVD”) or low pressurechemical vapor deposition (“LPCVD”).

The cap layer 120 in the example application may be implanted with anelectrically neutral species such as Ar. However, the cap layer 120 maybe implanted with other electrically neutral species such as Ge, As, andSb. Moreover, it is within the scope of the invention for the cap layerto be implanted with any dopant that causes structural damage to the caplayer 120 but is un-reactive with the silicon substrate 20, such as Ar.The sacrificial cap layer 120 is implanted with one or more of theseadditional dopants to facilitate an improved etch rate when the caplayer is removed, as described infra.

Referring again to the drawings, FIGS. 2A-2E are cross-sectional viewsof a partially fabricated semiconductor wafer 10 illustrating a processfor forming an example PMOS transistor 60 and NMOS transistor 70 inaccordance with the present invention. The following example applicationis exemplary but not restrictive of alternative ways of implementing theprinciples of the invention. Moreover, features and procedures whoseimplementations are well known to those skilled in the art are omittedfor brevity. For example, the implementation of common fabrication stepslies within the ability of those skilled in the art and accordingly anydetailed discussion thereof may be omitted.

FIG. 2A is a cross-sectional view of a semiconductor substrate 20containing partial PMOS and NMOS transistors 60, 70 that are formed withany standard manufacturing process. For example, a gate oxide layer anda gate polysilicon layer are initially formed over a semiconductorsubstrate 20 containing shallow trench isolation structures 50. Then,the gate oxide layer and the gate polysilicon layer are etched (using apatterned photoresist mask) to form the gate stacks of the PMOS and NMOStransistors 60, 70.

The extension regions 90 may be formed by low-energy ion implantation,gas phase diffusion, or solid phase diffusion. The dopants used tocreate the extension regions 90 for a PMOS transistor are p-type (i.e.boron). The dopants used to create the extension regions 90 for an NMOStransistor 70 are n-type (i.e. phosphorous and arsenic). In the exampleapplication, the gate stack 100, 110 is used as the mask to direct theplacement of the extension regions 90; however, extension sidewalls maybe formed proximate the gate stack 100, 110 and then used as a mask todirect the placement of the extension regions 90.

Next, source/drain sidewalls 130 are formed proximate to the gate stack100, 110. The example source/drain sidewalls 130 are comprised of alayer of nitride and a cap oxide; however, it Is within the scope of theinvention to use more layers (i.e. an L-shaped cap oxide layer, anL-shaped nitride layer, and a final oxide layer) or less layers (just asilicon oxide layer or just a silicon nitride layer) to create thesource/drain sidewalls 130. The gate stack 100, 110 and the source/drainsidewalls 110 are used as a template for the source/drain implant 140 ofdopants to form the source/drain regions 80. The source/drain regions 80may be formed by any standard implantation process, such as deep ionimplantation or deep diffusion. The dopants used to create thesource/drain regions 80 for a PMOS transistor are typically boron;however, other dopants or combinations for dopants may be used, Thedopants used to create the source/drain regions 80 for an NMOStransistor are typically phosphorous and arsenic; however, other dopantsor combinations for dopants may be used.

In accordance with the example embodiment, a sacrificial cap layer 120is now formed over the semiconductor wafer 10, as shown in FIG. 2B. Thecap layer 120 is preferably SIN; however, the cap layer 120 may becomprised of any suitable material such as SiON, SiC, SiOCN, or SiOC,The SIN cap layer 120 may have a thickness between 200-1000 Å and thethickness is preferably between 300-600 Å.

The cap layer 120 may be formed by any suitable process such as plasmaenhanced chemical vapor deposition (“PECVD”) using any suitable machinesuch as the Centura (sold by AMAT). In the example application, thePECVD process 150 uses silane and ammonia precursors, a pressure of 1-30Torr, a power level between 50 300 W, and a substrate temperature of250-450° C.. Alternatively, the cap layer 120 may be formed usinganother standard process, such as CVD or LPCVD (including BTBAS).

The next step in the fabrication process is a standard source/drainanneal 180, as shown in FIG. 2C. In the example application, thesource/drain regions 80 plus the extension regions 90 are activated bythe anneal step 160. This anneal step activates the dopants and repairsthe damage to the semiconductor wafer caused by the ion implants. Theactivation anneal may be performed by any conventional technique such asrapid thermal annealing (“RTA”) or spike annealing. However, the anneal160 is preferably performed by a millisecond anneal process such asflash lamp annealing (“FLA”) or laser annealing. Moreover, it is withinthe scope of the invention to use a combination of conventional andmillisecond anneals for step 160.

The anneal step 160 causes lateral and vertical migration of dopants inthe sources/drain regions 80 and the extension regions 90. In addition,the anneal step causes the full crystallization of the ion implant areas80, 90. If needed, a second anneal (which is generally similar to thefirst anneal), or multiple conventional and millisecond anneals, may beperformed to promote recrystallization and further lateral dopantmovement of the ion implant areas 80, 90.

The anneal 160 also causes the cap layer 120 to changestoichiometrically (by physically restructuring of the bonds of the caplayer 120). For the SiN cap layer 120 of the example application,hydrogen is released in the anneal process causing the atomic percent ofnitrogen and the atomic percent of silicon to increase, The result isthat the cap layer 120 will have an increased density (and a reducedthickness). Therefore, the compositional changes of the cap layer 120that occur during the anneal process causes the cap layer 120 to densityand transfer its stresses to the gate electrode 110.

The change in structure of the cap layer 120 (resulting from thesource/drain anneal 160) generally reduces the etch rate of the caplayer 120. As a result, it is sometimes difficult to thoroughly removethe cap layer 120 using standard wafer cleaning processes. Therefore, inaccordance with the example embodiment, the semiconductor wafer 10 issubjected to a blanket damage implant process 170 using a standard highcurrent implanter (sold by AMAT or Varian), as shown in FIG. 2D.

The damage implant 170 causes the cap layer 120 to be damaged, therebyincreasing the etch rate of the cap layer 120. In the exampleapplication, the cap layer 120 is implanted with an inert andelectrically neutral species such as Ar. However, it is within the scopeof the invention to implant other electrically neutral species such asGe, As, or Sb. It is also within the scope of the invention to implant acombination of species. Moreover, it is within the scope of theinvention to implant any species that will cause structural damage tothe cap layer 120 (and is preferably un-reactive with the siliconsubstrate 20).

Once the damage implant 170 is complete, the cap layer 120 is removed,as shown in FIG. 2E. In the example fabrication process, the cap layer120 is removed with a standard etch 180 such as a wet etch using hotphosphoric acid clean (H₃PO₄).

However, other standard cleaning processes may be used, such as a plasmadry etch (using a mixture of Cl₂/HBr/He/O₂). It is to be noted that thedamage implant 170 caused the etch rate of the cap layer 120 to beincreased; therefore, it is easier to remove the cap layer 120 with thestandard clean process 180. Moreover, the damage implant 170 may ensurethat the standard clean process 180 thoroughly removes the cap layer120.

The fabrication of the semiconductor wafer 10 now continues withstandard process steps until the semiconductor device is complete.Generally, the next step is the silicidation of the source/drain regions80 and gate electrode 110, the formation of the dielectric insulatorlayer, and then the formation of the contacts within the transistorlayer of the integrated circuit. The semiconductor wafer fabricationcontinues with the completion of the back-end structure that containsthe metal interconnects for electrically connecting the PMOS transistor60 and the NMOS transistor 70 to the remainder of the integratedcircuit. Once the fabrication process is complete, the integratedcircuit will be tested and then packaged.

FIGS. 3A-3E are cross-sectional views of a first alternative process forforming an example PMOS transistor 60 and NMOS transistor 70 inaccordance with the present invention. Specifically, the structuresshown in FIGS. 3A-3B are similar to the structures shown in FIGS. 2A-2B.The source/drain implant (140) is performed in FIG. 3A and the cap layer120 is formed (150) in FIG. 3B. However, in the first alternativeembodiment, the damage implant 170 is performed before the source/drainanneal (160), as shown in FIG. 3C. The damage implant 170 may be similarto the damage implant 170 described supra. Therefore, the dopant ispreferably Ar, but any inert or electrically neutral dopant may be used.However, in the example alternative application, the implant dosage isincreased (in order to obtain the targeted damage to the cap layer 120)because some of the dopants will be released (thereby reversing some ofthe damage to the cap layer 120) during the subsequent source/drainanneal 160 (of FIG. 3D).

As shown in FIG. 3D, the source/drain anneal 160 is performed uponcompletion of the damage implant 170, The source/drain anneal 160 issimilar to the source/drain anneal 160 described supra; therefore, thecap layer 120 will change composition, becoming densified and reduced inthickness.

In the first alternative fabrication process shown in FIG. 3E, the caplayer 120 is removed after the source/drain anneal 160 with a standardetch 180 such as a wet etch using hot phosphoric acid clean (H₃PO₄).However, other standard cleaning processes may be used, such as a plasmadry etch (using a mixture of Cl₂/HBr/He/O₂). It is to be noted that thedamage implant 170 (performed before the source/drain anneal 160) causedthe etch rate of the cap layer 120 to be increased; therefore, it iseasier to remove the cap layer 120 with a standard clean process 180. Inaddition, the damage implant 170 may ensure that the standard cleanprocess 180 will thoroughly remove the cap layer 120.

FIGS. 4A-4F are cross-sectional views of a second alternative processfor forming an example PMOS transistor 60 and NMOS transistor 70 inaccordance with the present invention. The structures shown in FIGS.4A-4D are similar to the structures shown in FIGS. 3A-3D. Thesource/drain implant (140) is performed in

FIG. 4A and the cap layer 120 is formed (150) in FIG. 4B. As shown inFIG. 4C, a first damage implant 170A is performed before thesource/drain anneal (160). The first damage implant 170A may be similarto the damage implants 170 described supra. Therefore, the dopant ispreferably Ar, but any inert or electrically neutral dopant may be used.However, in the example alternative application, the implant dosage isreduced (in order to ultimately obtain the targeted damage to the caplayer 120) because additional dopants will be implanted during a seconddamage implant 170E (as described infra).

Upon completion of the damage implant, the source/drain anneal 160 isperformed, as shown in FIG. 4D. The source/drain anneal 160 is similarto the source/drain anneals 160 described supra; therefore, the caplayer 120 will change composition—becoming densified and having areduced thickness.

In the second alternative fabrication process shown in FIG, 4E, a seconddamage implant 170B is performed after the source/drain anneal 160. Thesecond damage implant 170B may be similar to the damage implants 170described supra. Therefore, the dopant is preferably Ar, but any inertor electrically neutral dopant may be used. However, it is within thescope of the invention to use a different dopant for the second damageimplant 170B than was used for the first damage implant 170A. In theexample alternative application, the dosage of the second damage implant170B is the remaining dosage needed to obtain the targeted damage to thecap layer 120. In addition, the implant energy for the second damageimplant 170B of the example application is increased in order tofacilitate the implantation of dopants into the densified cap layer 120.The implant energies and doses for both implants are optimized to ensureadequate damage to the cap layer and facilitate its easy removal insubsequent cleaning steps. It is to be noted that it may be desirable touse a heavier dopant (such as Sb) for the second damage implant 170B inorder to better penetrate the denser cap layer 120 created by the firstdamage implant 170A.

The cap layer 120 is removed after the second damage implant 170B with astandard etch 180 such as a wet etch using hot phosphoric acid clean(H₃PO₄), as shown in FIG. 4F. However, other standard cleaning processesmay be used, such as a plasma dry etch (using a mixture ofCl₂/HBr/He/O₂). It is to be noted that the damage implants 170A and 170B(performed before and after the source/drain anneal 160) caused the etchrate of the cap layer 120 to be increased; therefore, it is easier toremove the cap layer 120 with a standard clean process 180. In addition,the damage implants 170A and 170B may ensure that the cap layer 120 isthoroughly removed with the standard clean process 180.

Various additional modifications to the invention as described above arewithin the scope of the claimed invention. As an example, the inventionmay be used during the fabrication of BiCMOS transistors, diodes, orpoly block resistors. Moreover, the cap layer 120 may contain additionallayers such as a silicon oxide liner film that is formed before the SiNlayer (to possibly enhance the transistor drive current).

Interfacial layers may be formed between any of the layers shown. Inaddition, an anneal process may be performed after any step in theabove-described fabrication process. For example, an anneal process maybe performed after the implantation of the extension regions 90 butbefore the implantation of the source/drain regions 80, When used, theanneal process can improve the microstructure of materials and therebyimprove the quality of the semiconductor structure.

While various embodiments of the present invention have been describedabove, it should be understood that they have been presented by way ofexample only, and not limitation. Numerous changes to the disclosedembodiments can be made in accordance with the disclosure herein withoutdeparting from the spirit or scope of the invention, Thus, the breadthand scope of the present invention should not be limited by any of theabove described embodiments. Rather, the scope of the invention shouldbe defined in accordance with the following claims and theirequivalents.

What is claimed is:
 1. An integrated circuit comprising: a silicon oxideliner film in contact with annealed source/drain regions and a gateelectrode of a transistor; and a cap layer comprising silicon andnitrogen in contact with said silicon oxide liner film; wherein said caplayer contains an electrically neutral species.
 2. integrated circuit ofclaim 1 wherein said electrically neutral species comprises Ar.
 3. Theintegrated circuit of claim 1 wherein said electrically neutral speciescomprises Sb.
 4. The integrated circuit of claim 1 wherein said caplayer also contains another electrically neutral species.
 5. Anintegrated circuit comprising: a silicon oxide liner film in contactwith annealed source/drain regions and a gate electrode of a transistor;and a cap layer comprising silicon and carbon in contact with saidsilicon oxide liner film; wherein said cap layer contains anelectrically neutral species.
 6. The integrated circuit of claim 5wherein said electrically neutral species comprises Ar.
 7. Theintegrated circuit of claim 5 wherein said electrically neutral speciescomprises Sb.
 6. The integrated circuit of claim 5 wherein said caplayer also contains another electrically neutral species.
 9. Anintegrated circuit comprising: a cap layer comprising silicon andnitrogen in contact with unannealed source/drain regions and a gateelectrode of a transistor; wherein said cap layer contains anelectrically neutral species.
 9. An integrated circuit of claim 9wherein said electrically neutral species comprises Ar.
 11. Anintegrated circuit comprising: a cap layer comprising silicon and carbonin contact with unannealed source/drain regions and a gate electrode ofa transistor; wherein said cap layer contains an electrically neutralspecies.
 12. The integrated circuit of claim 11 wherein saidelectrically neutral species comprises Ar.